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| HS-1212RH Data Sheet August 1999 File Number 4228.1 Radiation Hardened, Dual, High Speed Low Power, Video Closed Loop Buffer The HS-1212RH is a dual closed loop buffer featuring user programmable gain and high speed performance. Manufactured on Intersil's proprietary complementary bipolar UHF-1 (DI bonded wafer) process, this device offers wide -3dB bandwidth of 340MHz, very fast slew rate, excellent gain flatness and high output current. These devices are QML approved and are processed and screened in full compliance with MIL-PRF-38535. A unique feature of the pinout allows the user to select a voltage gain of +1, -1, or +2, without the use of any external components. Gain selection is accomplished via connections to the inputs, as described in the "Application Information" section. The result is a more flexible product, fewer part types in inventory, and more efficient use of board space. Compatibility with existing op amp pinouts provides flexibility to upgrade low gain amplifiers, while decreasing component count. Unlike most buffers, the standard pinout provides an upgrade path should a higher closed loop gain be needed at a future date. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-96831. A "hot-link" is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp Features * Electrically Screened to SMD # 5962-96831 * QML Qualified per MIL-PRF-38535 Requirements * MIL-PRF-38535 Class V Compliant * User Programmable For Closed-Loop Gains of +1, -1 or +2 Without Use of External Resistors * Standard Operational Amplifier Pinout * Low Supply Current . . . . . . . . . . . . 5.9mA/Op Amp (Typ) * Excellent Gain Accuracy . . . . . . . . . . . . . . . 0.99V/V (Typ) * Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . .340MHz (Typ) * Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . .1155V/s (Typ) * High Input Impedance . . . . . . . . . . . . . . . . . . . 1M (Typ) * Excellent Gain Flatness (to 50MHz). . . . . . 0.02dB (Typ) * Fast Overdrive Recovery . . . . . . . . . . . . . . . . <10ns (Typ) * Total Gamma Dose. . . . . . . . . . . . . . . . . . . . 300kRAD(Si) * Latch Up . . . . . . . . . . . . . . . . . . . . . None (DI Technology) Applications * Flash A/D Driver * Video Switching and Routing * Pulse and Video Amplifiers * Wideband Amplifiers * RF/IF Signal Processing * Imaging Systems Ordering Information ORDERING NUMBER 5962F9683101VPA 5962F9683101VPC INTERNAL MKT. NUMBER HS7-1212RH-Q HS7B-1212RH-Q TEMP. RANGE (oC) -55 to 125 -55 to 125 Pinout HS-1212RH (CERDIP) GDIP1-T8 OR HS-1212RH (SBDIP) CDIP2-T8 TOP VIEW OUT1 -IN1 +IN1 V- 1 -+ 2 3 4 +- 8 7 6 5 V+ OUT2 -IN2 +IN2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999 HS-1212RH Application Information HS-1212RH Advantages The HS-1212RH features a novel design which allows the user to select from three closed loop gains, without any external components. The result is a more flexible product, fewer part types in inventory, and more efficient use of board space. Implementing a dual, gain of 2, cable driver with this IC eliminates the four gain setting resistors, which frees up board space for termination resistors. Like most newer high performance amplifiers, the HS-1212RH is a current feedback amplifier (CFA). CFAs offer high bandwidth and slew rate at low supply currents, but can be difficult to use because of their sensitivity to feedback capacitance and parasitics on the inverting input (summing node). The HS-1212RH eliminates these concerns by bringing the gain setting resistors on-chip. This yields the optimum placement and value of the feedback resistor, while minimizing feedback and summing node parasitics. Because there is no access to the summing node, the PCB parasitics do not impact performance at gains of +2 or -1 (see "Unity Gain Considerations" for discussion of parasitic impact on unity gain performance). The HS-1212RH's closed loop gain implementation provides better gain accuracy, lower offset and output impedance, and better distortion compared with open loop buffers. Table 1 lists five alternate methods for configuring the HS-1212RH as a unity gain buffer, and the corresponding performance. The implementations vary in complexity and involve performance trade-offs. The easiest approach to implement is simply shorting the two input pins together, and applying the input signal to this common node. The amplifier bandwidth decreases from 430MHz to 280MHz, but excellent gain flatness is the benefit. A drawback to this approach is that the amplifier input noise voltage and input offset voltage terms see a gain of +2, resulting in higher noise and output offset voltages. Alternately, a 100pF capacitor between the inputs shorts them only at high frequencies, which prevents the increased output offset voltage but delivers less gain flatness. Another straightforward approach is to add a 620 resistor in series with the amplifier's positive input. This resistor and the HS-1212RH input capacitance form a low pass filter which rolls off the signal bandwidth before gain peaking occurs. This configuration was employed to obtain the data sheet AC and transient parameters for a gain of +1. Pulse Overshoot The HS-1212RH utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased overshoot on the negative portion of the output waveform (see Figure 6, Figure 9, and Figure 12). This overshoot isn't present for small bipolar signals (see Figure 4, Figure 7, and Figure 10) or large positive signals (see Figure 5, Figure 8 and Figure 11). Closed Loop Gain Selection This "buffer" operates in closed loop gains of -1, +1, or +2, with gain selection accomplished via connections to the inputs . Applying the input signal to +IN and floating -IN selects a gain of +1 (see next section for layout caveats), while grounding -IN selects a gain of +2. A gain of -1 is obtained by applying the input signal to -IN with +IN grounded through a 50 resistor. The table below summarizes these connections: GAIN (ACL) -1 +1 +2 CONNECTIONS +INPUT 50 to GND Input Input -INPUT Input NC (Floating) GND PC Board Layout This amplifier's frequency response depends greatly on the care taken in designing the PC board (PCB). The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10F) tantalum in parallel with a small value (0.1F) chip capacitor works well in most cases. Unity Gain Considerations Unity gain selection is accomplished by floating the -Input of the HS-1212RH. Anything that tends to short the -Input to GND, such as stray capacitance at high frequencies, will cause the amplifier gain to increase toward a gain of +2. The result is excessive high frequency peaking, and possible instability. Even the minimal amount of capacitance associated with attaching the -Input lead to the PCB results in approximately 6dB of gain peaking. At a minimum this requires due care to ensure the minimum capacitance at the -Input connection. 2 HS-1212RH TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS APPROACH Remove -IN Pin +RS = 620 +RS = 620 and Remove -IN Pin Short +IN to -IN (e.g., Pins 2 and 3) 100pF Capacitor Between +IN and -IN PEAKING (dB) 4.5 0 0.5 0.6 0.7 BW (MHz) 430 220 215 280 290 0.1dB GAIN FLATNESS (MHz) 21 27 15 70 40 Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. An example of a good high frequency layout is the Evaluation Board shown in Figure 3. Evaluation Board The performance of the HS-1212RH may be evaluated using the HA5023 Evaluation Board, slightly modified as follows: 1. Remove the two feedback resistors, and leave the connections open. 2. a. For AV = +1 evaluation, remove the gain setting resistors (R1), and leave pins 2 and 6 floating. b. For AV = +2, replace the gain setting resistors (R1) with 0 resistors to GND. The modified schematic for amplifier 1, and the board layout are shown in Figures 2 and 3. To order evaluation boards (part number HA5023EVAL), please contact your local sales office. Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier's phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 350MHz. By decreasing RS as CL increases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth decreases as the load capacitance increases. 50 SERIES OUTPUT RESISTANCE () 50 OUT R 1 (NOTE) IN 50 1 2 3 4 - + 8 7 6 5 GND GND 0.1F +5V 10F -5V 10F 0.1F NOTE: R1 = (AV = +1) OR 0 (AV = +2) FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC 40 30 20 AV = +2 10 AV = +1 0 0 50 100 150 200 250 300 350 400 LOAD CAPACITANCE (pF) FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD CAPACITANCE 3 HS-1212RH FIGURE 3A. TOP LAYOUT FIGURE 3. EVALUATION BOARD LAYOUT FIGURE 3B. BOTTOM LAYOUT Typical Performance Curves 200 150 OUTPUT VOLTAGE (mV) AV = +2 VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified 2.0 AV = +2 1.5 OUTPUT VOLTAGE (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) TIME (5ns/DIV.) FIGURE 4. SMALL SIGNAL PULSE RESPONSE FIGURE 5. LARGE SIGNAL POSITIVE PULSE RESPONSE 2.0 AV = +2 1.5 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) 200 150 100 50 0 -50 -100 -150 -200 AV = +1 TIME (5ns/DIV.) FIGURE 6. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 7. SMALL SIGNAL PULSE RESPONSE 4 HS-1212RH Typical Performance Curves 2.0 AV = +1 1.5 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued) 2.0 AV = +1 FIGURE 8. LARGE SIGNAL POSITIVE PULSE RESPONSE FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE 200 AV = -1 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200 2.0 AV = -1 1.5 OUTPUT VOLTAGE (V) TIME (5ns/DIV.) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) FIGURE 10. SMALL SIGNAL PULSE RESPONSE FIGURE 11. LARGE SIGNAL POSITIVE PULSE RESPONSE 2.0 AV = -1 1.5 OUTPUT VOLTAGE (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) NORMALIZED GAIN (dB) 6 3 0 -3 -6 -9 PHASE GAIN AV = +2 NORMALIZED PHASE (DEGREES) AV = +1 AV = -1 0 -90 AV = +1 AV = +2 -180 -270 -360 600 VOUT = 200mVP-P +RS = 620 (+1) +RS = 0 (-1, +2) 1 10 100 FREQUENCY (MHz) FIGURE 12. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 13. FREQUENCY RESPONSE 5 HS-1212RH Typical Performance Curves VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued) NORMALIZED GAIN (dB) 6 3 NORMALIZED GAIN (dB) 0 -3 -6 -9 AV = -1 AV = +2 AV = +1 VOUT = 4VP-P (+1) VOUT = 5VP-P (-1, +2) +RS = 620 (+1) 1 10 FREQUENCY (MHz) 100 300 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 1 AV = +1 10 FREQUENCY (MHz) AV = -1 100 AV = +2 VOUT = 200mVP-P +RS = 620 (+1) +RS = 0 (-1, +2) FIGURE 14. FULL POWER BANDWIDTH FIGURE 15. GAIN FLATNESS -10 -20 -30 CROSSTALK (dB) -40 GAIN (dB) -50 -60 -70 -80 -90 -100 -110 0.3 1 10 FREQUENCY (MHz) AV = +2 100 AV = +1 AV = -1 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0.3 1 10 FREQUENCY (MHz) 100 500 RL = 100 RL = AV = +2 FIGURE 16. REVERSE ISOLATION FIGURE 17. ALL HOSTILE CROSSTALK -40 -45 20MHz DISTORTION (dBc) -50 -55 10MHz -60 -65 -70 -10 DISTORTION (dBc) -40 -45 -50 20MHz -55 -60 10MHz -65 -70 -10 -5 0 5 10 15 -5 OUTPUT POWER (dBm) 0 5 OUTPUT POWER (dBm) 10 15 FIGURE 18. 2nd HARMONIC DISTORTION vs POUT FIGURE 19. 3rd HARMONIC DISTORTION vs POUT 6 HS-1212RH Typical Performance Curves 0.10 AV = +1 NOISE CURRENT (pA/Hz) NOISE VOLTAGE (nV/Hz) 16 16 VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued) 20 20 SETTLING ERROR (%) 0.05 0 12 12 -0.05 8 ENI 8 -0.10 4 I NI 0 0.1 4 13 33 53 73 93 113 TIME (ns) 133 153 173 1 10 FREQUENCY (kHz) 0 100 FIGURE 20. SETTLING RESPONSE FIGURE 21. INPUT NOISE CHARACTERISTICS 3.6 3.5 OUTPUT VOLTAGE (V) 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 -50 -25 0 25 50 75 100 125 +VOUT (RL= 50) |-VOUT| (RL= 50) AV = -1 |-VOUT| (RL= 100) +VOUT (RL= 100) TEMPERATURE (oC) FIGURE 22. OUTPUT VOLTAGE vs TEMPERATURE 7 HS-1212RH Burn-In Circuit HS-1212RH CERDIP D3 1 -+ 2 D4 R1 VD2 C2 3 4 +7 6 5 R1 8 C1 D1 V+ NOTES: 1. R1 = 1k, 5% (Per Socket). 2. C1 = C2 = 0.01F (Per Socket) or 0.1F (Per Row) Minimum. 3. D1 = D2 = 1N4002 or Equivalent (Per Board). 4. D3 = D4 = 1N4002 or Equivalent (Per Socket). 5. |(-V)| + |(+V)| = 11V 1.0V. 6. 10mA < | ICC, IEE | < 16mA. 7. -50mV < VOUT < +50mV. Irradiation Circuit HS-1212RH CERDIP 1 -+ 2 R1 3 VC1 4 +- 8 7 6 R1 5 C1 V+ NOTES: 8. R1 = 1k, 5% 9. C1 = 0.01F 10. V+ = +5.0V 0.5V 11. V- = -5.0V 0.5V 8 HS-1212RH Die Characteristics DIE DIMENSIONS: 69 mils x 92 mils x 19 mils 1750m x 2330m x 483m INTERFACE MATERIALS: Glassivation: Type: Nitride Thickness: 4kA 0.5kA Top Metallization: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kA 0.4kA Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kA 0.8kA Substrate: UHF-1X, Bonded Wafer, DI Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential (Powered Up): Floating (Recommend Connection to V-) ADDITIONAL INFORMATION: Transistor Count: 180 Metallization Mask Layout HS-1212RH -IN1 OUT1 NC V+ NC +IN1 OUT2 NC NC -IN2 NC V- NC +IN2 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 9 |
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